What was it about, and does it matter today?
This is a long article, so here's some mellow 80s synth pop to listen to while you're reading, from an appropriately named band. I like the restored version of the album. FYI The rest of the references are real...
https://mainframe-music.info/index.htmlThe Case for the Reduced Instruction Set Computer - D. Patterson / D. Ditzel.
https://people.cs.umass.edu/~emery/classes/cmpsci691st/readings/Arch/RISC-patterson.pdfPaper describing the Berkeley RISC-I processor.
RISC I: A Reduced Instruction Set VLSI Computer - D. Patterson / C. Sequin.
https://people.eecs.berkeley.edu/~kubitron/courses/cs252-S07/handouts/papers/p216-patterson.pdfRetrospective: RISC 1: Reduced Instruction Set Computer - D. Patterson / C. Sequin.
https://www.researchgate.net/publication/220771227_Retrospective_RISC_I_A_Reduced_Instruction_Set_Computer8086 microcode is complex stuff - and the 8086 is relatively simple!
How the 8086 processor's microcode engine works - K. Shirriff.
https://www.righto.com/2022/11/how-8086-processors-microcode-engine.htmlDesign Philosophy Behind Motorola's MC68000 - T. Starnes.
http://www.easy68k.com/paulrsm/doc/dpbm68k1.htmRetrospective on High-Level Language Computer Architecture - D. Ditzel / D. Patterson.
https://people.eecs.berkeley.edu/~kubitron/cs252/handouts/papers/p97-ditzel.pdfThe evolution of RISC technology at IBM - J. Cocke / V. Markstein.
https://acg.cis.upenn.edu/milom/cis501-Fall11/papers/cocke-RISC.pdfArchitectural Tradeoffs in the Design of MIPS-X - P. Chow / M. Horrowitz.
https://archive.org/details/DTIC_ADA182299Definition from the Computer Architecture Bible:
Computer Architecture: A Quantitative Approach - J. Hennessy / D. Patterson.A deep dive into CISC and RISC instruction set complexity - J. Mashey.
https://homepages.cwi.nl/%7Erobertl/mash/RISCvsCISCProposal for upping the number of x86 registers to 32 - X86 Ecosystem advisory group.
https://x86ecosystem.org/blog/apx-201/Conference slides - D. Ditzel.
https://microarch.org/micro55/media/keynote_ditzel.pdfIterative processor development at Bell labs - S. Johnson.
https://hoult.org/1979_Johnson_A_32_bit_Processor_Design.pdfTanenbaum Proposes Simpler Architecture in 1978.
Implications of Structured Programming for Machine Architecture - A. Tanenbaum.
https://research.vu.nl/ws/files/110789436/11056CDC 6600, the first supercomputer - HandWiki.
https://handwiki.org/wiki/CDC_6600Apple / NeXT 88110 development - Stories of Apple.
https://www.storiesofapple.net/the-88110-cpu-and-the-risc-workstations-that-never-were.htmlElectric Vlasic (pickle).
Characterisation of Organic Illumination Systems - Various.
https://web.archive.org/web/20080706151313/http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-TN-13.pdfM68060 User’s Manual - Motorola 1994.
https://www.nxp.com/docs/en/data-sheet/MC68060UM.pdfA History of The ARM Microprocessor - D. Jaggar (Talks at Google).
https://www.youtube.com/watch?v=_6sh097Dk5kList of SPEC 92 / 95 results from early/mid 90s.
https://www.cs.toronto.edu/pub/jdd/spectableAmiga Lightroom Benchmarks (FYI: My 2.8GHz Raspberry Pi 5 runs this in 47 seconds).
https://drive.google.com/file/d/1_VxGqSt2fMQbDxdZNO-SvA5Th0gfgp3n/view?pli=1Hombre, the future Amiga that never was :-(
https://grokipedia.com/page/Amiga_Hombre_chipsetFull Specs:
https://archive.org/details/Hombre_201808/Hombre_Presentation_part_1/Multi-core Alpha.
Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing - Various.
https://www.microsoft.com/en-us/research/wp-content/uploads/2016/12/isca00.piranha.pdfLex Fridman interviews David Patterson (includes RISC vs. CISC, RISC-V, and Wrestling).
https://www.youtube.com/watch?v=naed4C4hfAgDeep dive on the X925 core used in the RTX Spark.
Arm's Cortex X925: Reaching Desktop Performance - C. Lamb.
https://chipsandcheese.com/p/arms-cortex-x925-reaching-desktopSee below.
Nvidia Olympus Architecture
https://nvdam.widen.net/s/nmw5vblpqd/nvidia_vera_cpu_architecture_whitepaper?nvid=nv-tblg-543584Intel make chips for Apple, SpaceX and Nvidia.
href="https://www.macrumors.com/2026/07/13/apple-agreed-intel-chips-trump-tariff-talks/Amdahl's law
href="https://lawsofsoftwareengineering.com/laws/amdahls-law/x86 ecosystem advisory group.
https://x86ecosystem.org/Contemporary benchmark links:
SPECrate2026 integer base rate-1 (Estimated Performance):
https://benchview-hjc-im.translate.goog/?_x_tr_sl=auto&_x_tr_tl=en&_x_tr_hl=en-US&_x_tr_pto=wapp&_x_tr_hist=true#dataset=data%2FSPECrate2026_int_base.csvAbove is linked from David Huang's Blog:
https://blog.hjc.im/spec-cpu-2017PassMark Single Thread:
https://www.cpubenchmark.net/single-thread/Cinebench 2024 Scores:
https://www.cpu-monkey.com/en/cpu_benchmark-cinebench_2024_single_coreCinebench 2026 Single-threaded:
https://www.cpu-monkey.com/en/cpu_benchmark-cinebench_2026_single_threadGeekbench 6 Single-threaded:
https://www.cpu-monkey.com/en/cpu_benchmark-geekbench_6_single_coreEarly Nvidia Vera benchmarks, single + multi-threaded:
https://www.phoronix.com/review/nvidia-vera-benchmarksNote: Some of these terms are difficult to define as different vendors often use different terms and to add to the confusion they are often used interchangeably.
The 64 bit instruction set defined by Arm. AArch64 is the official name, Arm64 is more informal.
This determines how a value is interpreted in an instruction.
The company that defines the Arm architecture (i.e. instruction set architecture) and designs and licenses Arm processors (and more). Other companies such as Apple and Qualcomm design their own processors based on the Arm instruction set.
Note: "ARM" changed to "Arm" in a 2017 rebrand.
A small on-chip memory that is used to speed up access to data and instructions.
A sub-division of memory in a cache. The smallest contiguous block of memory that can be transferred between memory and cache.
How much memory a piece of code takes up. Variable length instructions typically have higher code density.
The stage where an instruction is interpreted. This determines what operation it represents.
An exception is an internal event triggered by the processor while executing an instruction. It tells the processor to stop what it's doing and deal with what caused the exception.
A fault is a type of exception. See Interrupt.
The stage where a processor gets (fetches) an instruction (or instructions) from memory into an internal buffer.
Describes the structure of an instruction.
The defined set of processor instructions and any effects they have.
An external signal that tells the processor to stop what it's doing and deal with what caused the interrupt. See exception.
The design or layout of the physical chip.
The basic operations that the processor performs. Many kinds of microprocessors, including RISC processors break instructions into micro-ops.
Memory is typically divided into multiple blocks called pages. This is used to enable multiple-users, multitasking, and security.
A type of code executed inside the processor. Usually involved in implementing an instruction, especially complex instructions.
Technique used by modern microprocessors to increase performance, involves executing instructions out of sequence where possible.
DEC's name for a technique similar to micro-code but typically much simpler.
Used in many processors, including RISC processors.
A series of stages of execution in a processor operating like an assembly line. This enables multiple instructions to be in different stages of execution simultaneously.
A small fast storage location inside a processor. Typically 32 or 64 bits long.
A processor that can issue more than one instruction per clock cycle.
Instructions whose size varies. These typically have high code density.
RISC vs. CISC at 46, Section A
RISC vs. CISC at 46, Section B
RISC vs. CISC at 46, Section C
RISC vs. CISC at 46, Section D
RISC vs. CISC at 46, Section E
© Nicholas Blachford 2026